1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a method for fabricating deep junction MOS transistors which suppresses device degradation due to hot-carrier injection and, thus, increases long term reliability.
2. Background of the Invention
Hot-carrier induced device degradation is becoming of more concern in the long term reliability of MOS circuit operation as the feature sizes of individual MOS transistors shrink.
Charge carrier velocity saturation effects are observed in shallow diffusion MOS devices with small channel lengths (less than about 3.5 microns) because of the high electric field strengths that result between source and drain under typical operating conditions. In the case of N-channel devices, with increasing applied gate voltage, the surface depletion region of the device continues to widen until the onset of surface inversion as electrons are attracted to the channel surface to form the inversion layer. Under these conditions, the electric field is such that electrons accelerating from the source towards the high drain potential strike the device lattice, generating an electron/hole pair. A portion of the "hot" electrons generated under these conditions are absorbed at the drain because of its high positive potential. The holes travel to the substrate, creating a substrate current. At the same time, the electrons become accelerated to the extent that, attracted by the high gate potential, they can overcome the barrier that exists between the substrate and the gate oxide, forming a gate current.
Because the injection efficiency mechanism is almost three orders of magnitude larger for N-channel devices than for P-channel devices, the problems associated with hot carrier injection are dominant in NMOS devices.
As a consequence of hot electron injection, localized traps are generated at the silicon/silicon dioxide interface which degrade transconductance. This degradation of the carrier mobility results in an upward shift of the threshold voltage of the device. Over the stressing conditions of long term operation, this shift in the device threshold results in premature device malfunction.
While a desire for higher density and faster devices has resulted in the almost exclusive use of self-aligned, shallow diffusion processing techniques in the formation of MOS transistors, the above-described problem of device degradation which occurs in these devices as channel lengths shrink and with the application of high voltage, potentially exceeding the standard supply, has created a need for an alternative in those applications where long term reliability is required.